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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. digital dc/dc pmbus 12a module zl9101m the zl9101m is a 12a variable output step-down pmbus-compliant digital power supply. included in the module is a high performance digital pwm controller, power mosfets, an inductor, and all the passive components required for a complete dc/dc power solution. the zl9101m operates over a wide input voltage range and supports an output voltage range of 0.6v to 4v, which can be set by external resistors or via pmbus. this high efficiency power module is capable of delivering 12a. only bulk input and output capacitors are needed to finish the design. the output voltage can be precisely regulated to as low as 0.6v with 1% output voltage regulation over line, load, and temperature variations. the zl9101m features internal compensation, internal soft-start, auto-recovery overcurrent protection, an enable option, and pre-biased output start-up capabilities. the zl9101m is packaged in a thermally enhanced, compact (15mmx15mm) and low profile (3.5mm) over-molded qfn package module suitable for automated assembly by standard surface mount equipment. the zl9101m is pb-free and rohs compliant. features ? complete digital switch mode power supply ? fast transient response ? external synchronization ? output voltage tracking ? current sharing ? programmable soft-start delay and ramp ? overcurrent/undercurrent protection ? pmbus compliant applications ?server, telecom, and datacom ? industrial and medical equipment ? general purpose point of load related literature ? see an2033 , ?zilker labs pmbus command set - ddc products? ? see an2034 , ?configuring current sharing on the zl2004 and zl2006? figure 1. 12a application circuit note: figure 1 represents a typical implementation of the zl9101m. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. v in 2 x 22f 16v i 2 c/smbus 1 power good output v out rtn 4.5v to 13.2v 3 x 47f 3 16v enable ddc bus 2 notes: 1. the i 2 c/smbus requires pull-up resistors. please refer to the i 2 c/smbus specifications for more details. 2. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the nu mber of devices connected). the 10k default value, assuming a maximum of 100pf per device, provides the necessary 1s pull-up rise time. please refer to the digital-dc bus section for more details. 3. additional capacitance may be required to meet specific transient response targets 4. the vr, v25, vdrv, and vdd capacitors should be placed no further than 0.5 cm from the pin. ext sync 10f 16v zl9101m sync sa scl sda vset vtrk fb+ vdrv vdd fb- pg ddc vr v25 sgnd en 4.7f 16v 4.7f 16v 10f 16v pgnd (epad) vin (epad) sw (epad) vout (epad) v drv 4.5v to 6.5v april 8, 2011 fn7669.2
zl9101m 2 fn7669.2 april 8, 2011 pin configuration zl9101m (21 ld qfn) top view sda vset vtrk fb+ fb- scl sa sync pg en ddc vr sgnd pgnd v25 vdd vdrv sw vin pgnd vout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 pin label type description 1sdai/oserial data. 2scli/oserial clock. 3 sa i serial address select pin. used to as sign unique smbus address to each module. 4 sync i/o clock synchronization. used for synchronization to external frequency reference. 5 pg o power-good output. 6 en i enable input (factory setting active high). pull-up to enable pwm switching and pull-down to disable pwm switching. 7 ddc i/o digital-dc bus. (open drain) interoperability between zilker labs modules. 8 vr pwr internal 5v reference used to power internal drivers. 9 sgnd pwr signal ground. connect to low impedance ground plane. 10 pgnd pwr power ground. connect to low impedance ground plane. 11 v25 pwr internal 2.5v reference used to power internal circuitry. 12 vdd pwr input supply voltage for controller. 13 vdrv pwr power supply for inte rnal fet drivers. connect 10 f bypass capacitor to this pin. 14(epad) sw pwr drive train switch node 15(epad) vin pwr power supply input fet voltage. 16(epad) pgnd pwr power ground. connect to low impedance ground plane. 17(epad) vout pwr power supply output voltage. output voltage from pwm. 18 fb- i output voltage feedback. connect to load return of ground regulation point. 19 fb+ i output voltage feedback. connect to output regulation point. 20 vtrk i tracking sense input. used to track an external voltage source. 21 vset i output voltage selection pin. used to set v out set point and v out max.
zl9101m 3 fn7669.2 april 8, 2011 ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # zl9101mirz zl9101m -40 to +85 21 ld 15x15 qfn l21.15x15 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil plastic packaged products employ special material sets, molding comp ounds and 100% matte tin plate plus anneal (e3) termination finish. these products do contain pb but they are rohs compliant by eu exemption 5 (pb in glass of cathode ray tubes, electroni c components and fluorescent tubes). these intersil rohs compliant products are co mpatible with both snpb and pb-free soldering operations. thes e intersil rohs compliant products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/j edec j std-020. 3. for moisture sensitivity level (msl), please see device information page for zl9101m . for more information on msl please see techbrief tb363 .
zl9101m 4 fn7669.2 april 8, 2011 table of contents related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 adaptive diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 i 2 c/smbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 i 2 c/smbus module address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 phase adding/dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 monitoring via i 2 c/smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 non-volatile memory and device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
zl9101m 5 fn7669.2 april 8, 2011 absolute maximum ratings (note 4) thermal information dc supply voltage for vdd pin . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15.7v input voltage for vin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 15.7v mosfet drive reference for vr pin . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v 2.5v logic reference for v25 pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v mosfet driver power for vdrv pin . . . . . . . . . . . . . . . . . . . . . .-0.3v to 7.5v logic i/o voltage for ddc, en, fb+, fb-, pg, sa, scl, sda,sync, vset pins . . . . . . . . . . . . . . . -0.3v to 6v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c110d) . . . . . . . . . . . 1000v latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) qfn package (notes 7, 8) . . . . . . . . . . . . . . 11.5 2.2 junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input supply voltage range, v in . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 13.2v input supply for controller, v dd (note 5) . . . . . . . . . . . . . . . . 4.5v to 13.2v driver supply voltage, v drv . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 6.5v output voltage range, v out (note 6). . . . . . . . . . . . . . . . . . . . . 0.54v to 4v output current range, i out(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 15a operating junction temperature range, t j . . . . . . . . . . . . . . . . . . . -40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. voltage measured with respect to sgnd 5. v in supplies the power fets. v dd supplies the controller. v in can be tied to v dd . for v dd 5.5v, v dd should be tied to vr. 6. includes 10% margin limits. 7. ja is simulated in free air with device mounted on a four-layer fr-4 test board (76.2 x 114.3 x 1.6mm) with 80%-coverage, 2-ounce cu on top and bottom layers, plus two, buried, one-ounce cu layers with covera ge across the entire test board area. multiple vias were used, with via diameter = 0.3mm on 1.2mm pitch. 8. for jc , the ?case? temperature is measured at the center of the package underside. electrical specifications v dd = 12 v, t a = -40c to +85c unless otherwise noted. typical values are at t a = 25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter conditions min (note 9) typ (note 10) max (note 9) unit input and supply characteristics input bias supply current, i dd f sw = 615khz, no load ? 20 40 ma input bias shutdown current, i dds en = 0 v no i 2 c/smbus activity ? 9.5 12 ma input supply current, i vin v in = 13.2v, i out = 15a, v out = 1.2v ? 1.5 2 a driver supply current, i vdrv not switching ? 190 220 a vr reference output voltage (note 11) v dd > 6v, i vr < 20ma 4.5 5.2 5.7 v v25 reference output voltage (note 11) v r > 3v, i v25 < 20ma 2.25 2.5 2.75 v output characteristics line regulation accuracy, v out / v in (note 12) v out = 1.2v, i out = 0a, v in = 5v to 13.2v ? 0.5 ? % load regulation accuracy, v out / i out (note 12) i out = 0a to 12a, v out = 1.2v ? 0.5 ? % peak-to-peak output ripple voltage, v out (note 12) i out = 12a, v out = 1.2v, c out = 3000f ? 6 ? mv soft-start delay duration range (notes 11, 13) set using i 2 c/smbus 2 ? 200 ms soft-start delay duration accuracy (note 11) turn-on delay (precise mode) (notes 13, 14) ? 0.25 - ms turn-on delay (normal mode) (note 15) ? -0.25/+4 - ms turn-off delay (note 15) ? -0.25/+4 - ms soft-start ramp duration range (note 11) set using i 2 c 0 ? 200 ms
zl9101m 6 fn7669.2 april 8, 2011 soft-start ramp duration accuracy (note 11) ? 100 ? s dynamic characteristics voltage change for positive load step i out = 6a, slew rate = 2.5a/ s, v out = 1.2v, c out = 3000f ? 3 ? % voltage change for negative load step i out = 6a, slew rate = 2.5a/ s, v out = 1.2v, c out = 3000f ? 3 ? % oscillator and switching characteristics (note 11) switching frequency range 590 615 630 khz maximum pwm duty cycle factory setting 95 ? ? % minimum sync pulse width 150 ? ? ns input clock frequency drift tolerance external clock source -13 ? 13 % logic input/output characteristics (note 11) logic input bias current en, pg, scl, sda pins -10 ? 10 a logic input low, v il ? ? 0.8 v logic input high, v ih 2.0 ? ? v logic output low, v ol i ol 4ma (note 17) ? ? 0.4 v logic output high, v oh i oh -2ma (note 17) 2.25 ? ? v fault protection characteristics (note 11) uvlo threshold range configurable via i 2 c/smbus 2.85 ? 16 v uvlo set-point accuracy -150 ? 150 mv uvlo hysteresis factory setting ? 3 ? % configurable via i 2 c/smbus 0 ? 100 % uvlo delay ? ? 2.5 s power good v out threshold factory setting ? 90 ? % v out power good v out hysteresis factory setting ? 5 ? % power good delay (note 16) configurable via i 2 c/smbus 0 ? 200 ms vsen undervoltage threshold factory setting ? 85 ? % v out configurable via i 2 c/smbus 0 ? 110 % v out vsen overvoltage threshold factory setting ? 115 ? % v out configurable via i 2 c/smbus 0 ? 115 % v out vsen undervoltage hysteresis ? 5 ? % v out vsen undervoltage/overvoltage fault response time factory setting ? 16 ? s configurable via i 2 c/smbus 5 ? 60 s electrical specifications v dd = 12 v, t a = -40c to +85c unless otherwise noted. typical values are at t a = 25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 9) typ (note 10) max (note 9) unit
zl9101m 7 fn7669.2 april 8, 2011 thermal protection threshold (controller junction temperature) factory setting ? 125 ? c configurable via i 2 c/smbus -40 ? 125 c thermal protection hysteresis ? 15 ? c notes: 9. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 10. parameters with typ limits are not production tested unless otherwise specified. 11. parameters are 100% tested for internal controller prior to module assembly. 12. v out measured at the termination of the fb+ and fb- sense points. 13. the device requires a delay period following an enable signal and prior to ramping its output. precise timing mode limits th is delay period to approximately 2ms, where in normal mode it may vary up to 4ms. 14. precise ramp timing mode is only valid when using th e en pin to enable the device rather than pmbus enable. 15. the devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-ass ertion of the enable signal. 16. factory setting for power good delay is set to the same value as the soft-start ramp time. 17. nominal capacitance of logic pins is 5pf. electrical specifications v dd = 12 v, t a = -40c to +85c unless otherwise noted. typical values are at t a = 25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 9) typ (note 10) max (note 9) unit typical performance curves figure 2. efficiency, v in = 6v figure 3. efficiency, v in = 9v figure 4. efficiency, v in = 12v figure 5. dynamic response, unloading 60 65 70 75 80 85 90 95 100 0246810121416 output current (a) efficiency (%) v in = 6v f sw = 615khz v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v 60 65 70 75 80 85 90 95 100 0246810121416 output current (a) efficiency (%) v in = 9v f sw = 615khz v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v 60 65 70 75 80 85 90 95 100 0246810121416 output current (a) efficiency (%) v in = 12v f sw = 615khz v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v -5 0 5 10 15 20 25 30 35 0 0.10.20.30.40.50.60.70.80.9 1 voltage deviation (mv) v in = 12v v out = 1.2v i out step = 12a to 6a slew 2.5a/s
zl9101m 8 fn7669.2 april 8, 2011 figure 6. dynamic response, loading figure 7. soft-start ramp-up figure 8. ramp-down typical performance curves (continued) -30 -25 -20 -15 -10 -5 0 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 voltage deviation (mv) v in = 12v v out = 1.2v i out step = 6a to 12a slew 2.5a/s -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t rise = 5ms v in = 12v -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t fall = 5ms v in = 12v derating curves figure 9a. derating curve, 5v in figure 9b. derating curve, 12v in 0 2 4 6 8 10 12 14 16 50 60 70 80 90 100 110 120 130 ambient temperature (c) max. load current (a) 1.0v out 3.3v out ambient temperature (c) 3.3v out 1.8v out 1.0v out 0 2 4 6 8 10 12 14 16 50 60 70 80 90 100 110 120 130 max. load current (a) 2.5v out
zl9101m 9 fn7669.2 april 8, 2011 functional description output voltage selection the output voltage may be set to a voltage between 0.6v and 4.0v provided that the input volt age is higher than the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. the vset pin is used to set the output voltage to levels as shown in table 1. the r set resistor is placed between the vset pin and sgnd. the output voltage may also be set to any value between 0.6v and 4.0v using a pmbus command over the i 2 c/smbus interface. see application note an2033 for details. soft-start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the zl9101m gives the system designer several options for precisely and independently controlling both the dela y and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay and ramp times are set to custom values via the i 2 c/smbus interface. when the delay time is set to 0ms, the device will begin its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft-sta rt ramp period is set to 0ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. it is generall y recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. power good the zl9101m provides a power good (pg) signal that indicates the output voltage is within a sp ecified tolerance of its target level and no fault condition exis ts. by default, the pg pin will assert if the output is within 10% of the target voltage. these limits and the polarity of th e pin may be changed via the i 2 c/smbus interface. see application note an2033 for details. a pg delay period is defined as the time from when all conditions within the zl9101m for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the zl9101m pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 10ms, the pg delay will be set to 10ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/smbus as described in application note an2033 . switching frequency and pll the zl9101m incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pl l can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source. the internal switching frequency of the zl9101m is 615khz. loop compensation the zl9101m operates as a voltage-mode synchronous buck controller with a fixed frequency pwm scheme. the module is internally compensated via the i 2 c/smbus interface. please refer to application note an2033 for further details. table 1. output voltage resistor settings v out (v) r set (k ? ) 0.60 10 0.65 11 0.70 12.1 0.75 13.3 0.80 14.7 0.85 16.2 0.90 17.8 0.95 19.6 1.00 21.5 1.05 23.7 1.10 26.1 1.15 28.7 1.20 31.6 1.25 34.8 1.30 38.3 1.40 42.2 1.50 46.4 1.60 51.1 1.70 56.2 1.80 61.9 1.90 68.1 2.00 75 2.10 82.5 2.20 90.9 2.30 100 2.50 110 2.80 121 3.00 133 3.30 147 4.00 162
zl9101m 10 fn7669.2 april 8, 2011 adaptive diode emulation adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the ener gy losses and increasing overall efficiency. diode emulation is available to single-phase devices only. note: the overall bandwidth of the device may be reduced when in diode emulation mode. it is recommended that diode emulation is disabled prior to applying significant load steps. input undervoltage lockout the input undervoltage lockout (uvlo) prevents the zl9101m from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85v and 16v using the i 2 c/smbus interface. once an input undervoltage faul t condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the module. the co ntroller will continuously check for the presence of the fault condition. if the fault condition is no longer present, the zl9101m will be re-enabled. please refer to application note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. output overvoltage protection the zl9101m offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescrib ed limits. a hardware comparator is used to compare the actual output voltage (seen at the fb+ pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the fb+ voltage exceeds this threshold, the pg pin will de-assert and the controller can then respond in a number of ways as follows: 1. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. the controller will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. for continuous overvoltage protection when operating from an external clock, the only allo wed response is an immediate shutdown. please refer to application note an2033 for details on how to select specific overvoltage fault response options via i 2 c/smbus. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at th e output. the zl9101m provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the preconfigured ramp rate. the actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapse d from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time. see figure 10. if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre-bias voltage. once the pre-configured soft-start ramp period has expired, the pg pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit) . the pwm will then adjust its figure 10. output responses to pre-bias voltages
zl9101m 11 fn7669.2 april 8, 2011 duty cycle to match the original target voltage and the output will ramp down to the preconfigured output voltage. if a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. in this case, the device will respond based on the output over voltage fault response method that has been selected. see ?output overvoltage protection? on page 10 for response options du e to an overvoltage condition. note that pre-bias protection is not offered for current sharing groups that also have tracking enabled. output overcurrent protection the zl9101m can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. the following ov ercurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown of the controller. the co ntroller will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. please refer to application note an2033 for details on how to select specific overcurrent fault response options via i 2 c/smbus. thermal overload protection the zl9101m includes a thermal sensor that continuously measures the internal temperat ure of the module and shuts down the controller when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the controller. once the module has been disabled due to an inte rnal temperature fault, the user may select one of several faul t response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the module to restart, the controller will wait the preset delay period (if configured to do so) and will then check the module temperature. if the temperature has dropped below a threshold that is approximately +15 c lower than the selected temperature fault limit, the controller will attempt to re-start. if the temper ature still exceeds the fault limit the controller will wait the preset delay period and retry again. the default response from a temp erature fault is an immediate shutdown of the module. the controller will continuously check for the fault condition, and once the fault has cleared the zl9101m will be re-enabled. please refer to application note an2033 for details on how to select specific temperature fault response options via i 2 c/smbus. i 2 c/smbus communications the zl9101m provides an i 2 c/smbus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. the zl9101m can be used with any i 2 c host device. in addition, the module is compatible with smbus version 2.0. pull-up resistors are required on the i 2 c/smbus as specified in the smbus 2.0 specification. the zl9101m accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the en able pin is tied to sgnd. i 2 c/smbus module address selection each module must have its own unique serial address to distinguish between other devices on the bus. the module address is set by connecting a resistor between the sa pin and sgnd. table 2 lists the available module addresses. table 2. smbus address resistor selection r sa0 smbus address 10 0x19 11 0x1a 12.1 0x1b 13.3 0x1c 14.7 0x1d 16.2 0x1e 17.8 0x1f 19.6 0x20 21.5 0x21 23.7 0x22 26.1 0x23 28.7 0x24 31.6 0x25 34.8 0x26 38.3 0x27 42.2 0x28 46.4 0x29 51.1 0x2a 56.2 0x2b
zl9101m 12 fn7669.2 april 8, 2011 digital-dc bus the digital-dc communications (ddc) bus is used to communicate between zilker labs digital-dc modules and devices. this dedicated bus prov ides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bu s in order to guarantee the rise time as follows: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as rules of thumb, each device connected to the ddc bus presents approximately 10p f of capacitive loading, and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design will use a central pull-up resistor that is well- matched to the total load capa citance. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8v at the device monitoring po int) given the pull-up voltage and the pull-down current capability of the zl9101m (nominally 4ma). phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronized to the same switching clock. the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/smbus interface. refer to application note an2033 for further details. output sequencing a group of digital-dc modules or devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fp gas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid la tch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface. multiple device sequencing is configured by issuing pmbus commands to assign the preced ing device in the sequencing chain as well as the device that will follow in the sequencing chain. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turnoff of the group. refer to application note an2033 for details on sequencing via the i 2 c/smbus interface. fault spreading digital dc modules and devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non- destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the dd c bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so. active current sharing paralleling multiple zl9101m modules can be used to increase the output current capability of a single power rail. by connecting the ddc pins of each module together and configuring the modules as a current sharing rail, the units will share the current equally within a few percent. figure 11 illustrates a typical connection for two modules. the zl9101m uses a low-bandwidth, first-order digital current sharing technique to balance the unequal module output loading by aligning the load lines of member modules to a reference module. droop resistance is used to add ar tificial resistance in the output voltage path to control the slope of the load line curve, 61.9 0x2c 68.1 0x2d 75 0x2e 82.5 0x2f 90.9 0x30 100 0x31 table 2. smbus address resistor selection (continued) r sa0 smbus address rise time r pu ? c load 1 s = (eq. 1) figure 11. current sharing group zl v out zl v in c out c in c out c in ddc ddc 3.3v - 5v
zl9101m 13 fn7669.2 april 8, 2011 calibrating out the physical parasitic mismatches due to power train components and pcb layout. upon system start-up, the module wi th the lowest member position as selected in ishare_config is defined as the reference module. the remaining modules are members. the reference module broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (v member ) to balance the current loading of each module in the system. figure 12 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by the following equation: where r is the value of the droop resistance. the ishare_config command is used to configure the module for active current sharing. the default setting is a stand-alone non-current sharing module. a current sharing rail can be part of a system sequencing group. for fault configuration, the curren t share rail is configured in a quasi-redundant mode. in this mode, when a member module fails, the remaining members will continue to operate and attempt to maintain regulation. of the remaining modules, the module with the lowest memb er position will become the reference. if fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. the phase offset of (multi-phase) current sharing modules is automatically set to a value between 0 and 337.5 in 22.5 increments as follows: please refer to application note an2034 for additional details on current sharing. phase adding/dropping the zl9101m allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. in doing so, the power converter is optimized at a load current range that requires all phases to be operational. during periods of ligh t loading, it may be beneficial to disable one or more phases in order to eliminate the current drain and switching losses asso ciated with those phases, resulting in higher efficiency. the zl9101m offers the ability to add and drop phases using a pmbus command in response to an observed load current change. all phases in a current sh are rail are considered active prior to the current sharing rail ramp to power-good. any member of the current sharing rail can be dropped. if the reference module is dropped, the remaining active module with the lowest member position wi ll become the new reference. additionally, any change to the number of members of a current sharing rail will precipitate autono mous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. if the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. monitoring via i 2 c/smbus a system controller can monitor a wide variety of different zl9101m system parameters through the i 2 c/smbus interface. the module can monitor for any number of power conversion parameters including but not limited to the following: ? input voltage/output voltage ?output current ? internal temperature ? switching frequency ? duty cycle please refer to application no te an2033 for details on how to monitor specific parameters via the i 2 c/smbus interface. snapshot parameter capture the zl9101m offers a special feature that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. see an2033 for details on using snapshot in addition to the parameters supported. the snapshot feature enables the user to read parameters via a block read transfer through the smbus. this can be done during normal op eration, although it should be noted that reading the 22 bytes will occupy the smbus for some time. the snapshot_control command enables the user to store the snapshot parameters to fl ash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. table 3 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any faul t threshold level is exceeded, provided that the specific faul t?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the module?s v dd voltage must be maintained during the time when the controller is writing the data to flash memory; -r -r v reference v member i member i reference i out v out figure 12. active current sharing () member reference out member i i r v v ? + = (eq. 2) phase offset smbus address 4:0 [] current ? = (eq. 3) share position ? 22.5
zl9101m 14 fn7669.2 april 8, 2011 a process that requires between 700s to 1400s depending on whether the data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. in the event that the module experiences a fault and power is lost, the user can extract the la st snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). non-volatile memory and device security features the zl9101m has internal non-volatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the module to a level that has been made available to them. during the initialization process, the zl9101m checks for stored values contained in its internal non-volatile memory. the zl9101m offers two internal me mory storage units that are accessible by the user as follows: 1. default store : the zl9101m has a default configuration that is stored in the default store in the controller. the module can be restored to its default settings by issuing a restore_default_all command over the smbus. 2. user store : the user can modify certain power supply settings as described in this data sheet. the user would use the user store to store their configuration. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/smbus interface. table 3. snapshot_control command data value description 1 copies current snapshot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot values to flash memory. only available when device is disabled.
zl9101m 15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7669.2 april 8, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: zl9101m to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/18/2011 fn7669.2 on page 1 in figure 1, changed vin in upper right from "5v to 12v" to "4.5v to 13.2v" in ?recommended operating conditions? on page 5: changed ?input supply voltage range, vin? from "5v to 13.2v" to "4.5v to 13.2v" changed ?input supply for controller, vdd? from "5v to 13.2v" to "4.5v to 13.2v" 1/20/2011 fn7669.1 on page 5 electrical spec table under input and supply characteristic - parameter ?input supply current, i vin ? conditions column changed from ?v in = 14v, i out = 15a, v out = 1.2v? to ?v in = 13.2v, i out = 15a, v out = 1.2v. under output characteristics - parameter ?line regu lation accuracy? conditio ns column changed from ?v out =1.2v, i out = 0a, v in = 5v to 14v? to ?v out = 1.2v, i out = 0a, v in = 5v to 13.2v?. 1/11/2011 on page 1, under features, changed "tracking" to "output voltage tracking" on page 1, figure 1, added footnote 4. "the vr, v25, vdrv, and vdd capacitors should be placed no further than 0.5 cm from the pin." on page 5, under ?absolute maximum ratings?, changed value: dc supply voltage for vdd pin from 16v to 15.7v on page 5, under ?absolute maximum ratings?, changed value: input voltage for vin pin from 16v to 15.7v on page 5, under recommended operating conditions, ch anged value: input supply voltage range, vin from 14v to 13.2v on page 5, under recommended operating conditions, ch anged value: input supply for controller, vdd from 14v to 13.2v on page 7, note 11, changed "... for internal ic prior ..." to "... for internal controller prior ..." on page 8, figure 7, changed title from ?ramp-up? to "soft-start ramp-up" on page 8, figure 9a, change d labels to from v to v out (e.g. 3.3v out, 1.0v out ) on page 8, figure 9b, changed labels to from v to v out (e.g. 3.3v out, 1.0v out ) 12/20/2010 fn7669.0 initial release
zl9101m 16 fn7669.2 april 8, 2011 package outline drawing l21.15x15 21 lead quad flat no-lead plastic package (punch qfn) rev 0, 10/10 bottom view side view top view s 0.2 5 a l l a r o u n d s s 0.05 3.50.2 0.50 13 15.00.2 15.80.2 10 11 12 14 15 index area pin 1 18 9 8 6 7 4 5 2 3 1 21 19 20 16 15.00.2 15.80.2 17 2.95 5.65 4.65 2.0 8x 1.80.05 13 12 10 11 0.05 33x 0.5 17x 0.80 4.40 1.95 12.05 2.95 8.3 15 16 14 1.3 3.1 4.2 0.8 17 6.3 7.25 18 19 21 20 a b 9 8 6 7 4 5 17x 0.75 9x 1.90.05 2 3 1 x4 b:2.6 0.1 a:1.3 0.1 c:1.13 0.1 13 15 b a a a a aa aa aa a 14 16 9 c c b 12 11 10 a aa a a b a 6 8 7 4 5 2 3 b 18 aa a 17 a a a b 19 20 1 21 a s ab 0.2 s ab
zl9101m 17 fn7669.2 april 8, 2011 stencil pattern with square pads-2 typical recommended land pattern stencil pattern with square pads-1 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.2; the configuration of the pin #1 iden tifier is optional, but must be 3. either a mold or mark feature. 2. dimensions are in millimeters. 1. notes: body tolerance 0.2mm 0.0 0.0 3.8 5.8 4.4 1.2 1.8 0.0 2 1 21 5.7 5.5 1.7 3.0 6.1 8.3 5.6 6.0 4.8 0.4 1.7 2.2 0.9 0.4 0.0 0.9 6.2 7.0 4.3 3.0 2.2 3.5 5.6 4.8 6.0 4.2 6.9 0.0 3.4 4.2 4.7 0.7 3.0 2.2 1.4 0.1 0.6 4.8 2.2 5.6 5.6 8.3 8.3 4.1 4.9 0.3 0.0 1.1 8.3 4.2 0.1 0.6 0.7 3.1 2.3 4.9 4.4 3.6 0.0 6.9 2 21 1 5.6 5.0 6.9 8.3 4.8 3.0 2.4 0.7 2.5 4.5 4.2 6.3 5.8 6.5 2.2 5.1 6.4 3.8 1.4 0.05 1.6 0.0 0.8 3.9 6.4 5.3 3.0 2.9 1.6 4.0 3.4 0.9 6.5 2.9 5.5 6.1 4.9 5.4 6.2 4.1 4.8 3.5 0.3 1.6 2.3 1.0 0.3 0.0 1.0 3.7 5.6 6.3 5.0 4.3 6.9 4.2 2.9 2.3 3.6 5.5 4.9 6.1 1 2 21 2.3 2.8 0.0 2.3 0.6 2.3 1.3 0.7 6.1 4.1 3.5 8.2 6.7 3.6 8.2 5.1 6.8 5.5 4.0 0.3 2.3 2.9 1.0 1.6 0.1 0.0 1.2 1.6 8.2 6.8 2.8 3.5 4.1 0.9 1.5 0.6 0.0 0.0 2.4 2.2 5.1 3.6 2.9 4.0 8.2 6.8 5.5

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